Scheme for detecting CMOS stuck-open faults using single test patterns

A technique for detection of stuck-open faults in CMOS circuits is presented. This approach needs only a single test pattern for detecting such faults, and the circuit retains its combinational characteristic. The problem of test invalidation by circuit delays, timing skews, etc., has been eliminated. Only two transistors and an additional input are needed to make any gate fully testable for all single stuck-open faults. Hence the area overhead is not significant. With a slight modification and a slightly greater increase in overhead the technique can be extended to detection of s-closed faults as well