0.18 μm CMOS low noise amplifier for 3-5 GHz ultra-wideband system

A single-stage and cascode stage wideband CMOS low noise amplifier (LNA) that uses the inductive source degeneration network are presented in this paper. The proposed LNAs are implemented in 0.18 μm CMOS technology for a 3-5GHz ultra-wideband system. The proposed single-stage LNA achieves a simulated maximum power gain of +9.25dB, minimum noise figure of 3.2dB, minimum return loss of -6.7dB, input-referred ldB gain compression point of -5.11dBm and input third order intercept point of +3.36dBm while consuming 6.25mW of DC dissipation at a DC supply of V. Simulation results for the proposed cascode stage LNA show a maximum power gain of +12.3dB, a minimum noise figure of 3.2dB, a minimum return loss of -5.1dB, an input PldB of -13dBm and an IIP3 of -4.2dBm, while consuming 10.5mW of DC dissipation with a DC supply of 1.5V. Results obtained from this study can used as reference design for current multi-stage UWB LNAs implementation.