• DocumentCode
    2908477
  • Title

    Using cache to reduce power in content-addressable memories (CAMs)

  • Author

    Pagiamtzis, Kostas ; Sheikholeslami, Ali

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.
  • fYear
    2005
  • fDate
    21-21 Sept. 2005
  • Firstpage
    369
  • Lastpage
    372
  • Abstract
    We propose using caching to save power in content-addressable memories (CAMs). By using a small cache along with the CAM, we avoid accessing the larger and higher power CAM. For a cache hit rate of 90%, the cache-CAM (C-CAM) saves 80% power over a conventional CAM, for a cost of 15% increase in silicon area. Even at a low hit rate of 50%, a power savings of 40% is achieved. The proposed C-CAM is employed in the design of a testchip demonstrating a 2.6 fJ/bit/search in a 0.18 mum CMOS process
  • Keywords
    CMOS memory circuits; cache storage; content-addressable storage; elemental semiconductors; silicon; 0.18 micron; CMOS process; Si; cache CAM; caching technique; content-addressable memories; power savings; CADCAM; Cams; Circuits; Computer aided manufacturing; Costs; Energy consumption; Pipelines; Power dissipation; Silicon; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7803-9023-7
  • Type

    conf

  • DOI
    10.1109/CICC.2005.1568682
  • Filename
    1568682
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2908477