A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35 mum BiCMOS process. The ADC has an input switched buffer and 11 pipeline stages. The sample-and-hold circuit is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier. Measured results on silicon indicate the highest performance to date (in SNR, SFDR, DNL and INL) at this sample rate and over the whole input frequency range up to 500 MHz. The ADC achieves a DNL of less than 0.2 LSB and INL of less than 0.5 LSB. The SNR is 75 dB below Nyquist, 73 dB at 300 MHz, and 72 dB at 400 MHz. The SFDR is 100 dB below Nyquist, 89 dB at 300 MHz, and 82 dB at 400 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a jitter of only 50 fs