• DocumentCode
    2908561
  • Title

    Novel 10-T full adders realized by GDI structure

  • Author

    Lee, Po-Ming ; Hsu, Chia-Hao ; Hung, Yun-Hsiun

  • Author_Institution
    Southern Taiwan Univ. of Technol., Taipei
  • fYear
    2007
  • fDate
    26-28 Sept. 2007
  • Firstpage
    115
  • Lastpage
    118
  • Abstract
    A full adder is one of the most commonly used digit circuit components, many improvements have been made to refine the architecture of a full adder. In this paper, 4 different types of 10 transistor (10-T) based full adder are proposed using a new design methodology called GDI (gate-diffusion input). In the meantime, a complete verification and comparison is also carried out to test the performance of the proposed adders. According to our test results, one of the proposed 10-T full adders is better than the prior designs which makes it a better alternative.
  • Keywords
    CMOS logic circuits; adders; 10-T full adder; CMOS logic; GDI structure; gate-diffusion input; Adders; CMOS logic circuits; CMOS process; Design methodology; Equations; Logic devices; Pins; Silicon on insulator technology; TV; Testing; CMOS; Full Adder; GDI;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits, 2007. ISIC '07. International Symposium on
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-0797-2
  • Electronic_ISBN
    978-1-4244-0797-2
  • Type

    conf

  • DOI
    10.1109/ISICIR.2007.4441810
  • Filename
    4441810