DocumentCode :
2908652
Title :
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack
Author :
Mehdipour, Farhad ; Nunna, Krishna Chaitanya ; Gauthier, Lovic ; Inoue, Koji ; Murakami, Kazuaki
Author_Institution :
E-JUST Center, Kyushu Univ., Fukuoka, Japan
fYear :
2012
fDate :
Jan. 31 2012-Feb. 2 2012
Firstpage :
1
Lastpage :
4
Abstract :
Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.
Keywords :
cooling; flow graphs; thermal management (packaging); three-dimensional integrated circuits; 3D stack; accelerator; base processor; data flow graphs; data-path accelerator; heat dissipation; memory components; peak temperature reduction; processing elements; thermal management; thermal-aware mapping algorithm; thermal-aware partitioning; three-dimensional integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
Type :
conf
DOI :
10.1109/3DIC.2012.6263034
Filename :
6263034
Link To Document :
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