A consistent physical model for the gate-leakage and breakdown in InAlAs/InGaAs HFETs

The improvement of the speed performance of Heterostructure Field-Effect Transistors (HFET) by increasing the channel indium content is accompanied by impact ionization degrading the gate leakage and the breakdown behaviour, among others. A physical understanding of the impact of the layer stack and fabrication process is prerequisite for limiting these drawbacks to a certain amount. Here we will provide for the first time a full analytical expression for the leakage current and for the gate-drain breakdown voltage in dependence on the epitaxy layer design and the recess procedure technique. These formulas, based on a physical model including a novel bias dependent velocity approach to simulate the velocity overshoot, are verified with high quality, kink-free InP-based HFETs