Phase change RAM operated with 1.5-V CMOS as low cost embedded memory

This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for reset/set/read operations based on measurement results and identified that it is impossible to distinguish between reset/set operations by controlling the bit-line voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate set operations. Moreover, we investigated the read disturb operation and developed a new reduced-actual-read-access (RA2) scheme to attain 500 times the read retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F² memory cell with enough reset current to clearly reset the PC material. With the application of these approaches, we established reset/set/read operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks.