Title :
A capacitorless twin-transistor random access memory (TTRAM) on SOI
Author :
Morishita, Fukashi ; Noda, Hideyuki ; Gyohten, Takayuki ; Okamoto, Mako ; Ipposhi, Takashi ; Maegawa, Shigeto ; Dosaka, Katsumi ; Arimoto, Kazutami
Author_Institution :
Syst. Core Technol. Div., Renesas Technol. Corp., Hyogo, Japan
Abstract :
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80°C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1ns row-access time is achieved and 250MHz operation can be realized by using 2bank 8b-burst mode.
Keywords :
CMOS memory circuits; random-access storage; silicon-on-insulator; 100 ms; 130 nm; 2 Mbit; 250 MHz; 6.1 ns; 8 bit; 80 C; SOI-CMOS process; TTRAM cells; capacitorless random access memory; data retention time; data-storage states; row-access time; twin-transistor random access memory; CMOS process; Capacitors; Energy consumption; Random access memory; Testing; Tin; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568699
