Pre-bond testing of die logic and TSVs in high performance 3D-SICs

3D integrated circuits based on die stacking and through-silicon vias (TSVs) present a number of significant test challenges. Pre-bond testing of TSVs and partial logic on a die are especially difficult problems. This paper addresses pre-bond probing of TSVs and the testing of die logic before and after TSV breakpoints. By utilizing CMOS-compatible fuses, the functional overhead of test circuitry required for this testing can be reduced by disconnecting unnecessary fanout from functional paths after testing. Simulation results show significant reduction in functional delay when utilizing our architecture when compared to other methods.