A high speed superscalar PA-RISC processor

Author

Delano, Eric ; Walker, Will ; Yetter, Jeff ; Forsyth, Mark

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

1992

fDate

24-28 Feb. 1992

Firstpage

116

Lastpage

121

Abstract

A novel processor implementing Hewlett-Packard´s PA-RISC 1.1 (precision architecture-reduced instruction set computer) has been designed. A single chip implemented in a 0.8- mu m three-level metal CMOS technology includes the integer processor and a floating point coprocessor. The design operates at 100 MHz and is the first superscalar PA-RISC design. The processor cache is a large configurable memory implemented with industry standard SRAMs (static RAMs). High performance is achieved by high-frequency operation and a variety of techniques used to reduce the average number of cycles per instruction.<>

Keywords

CMOS integrated circuits; digital arithmetic; microprocessor chips; reduced instruction set computing; 0.8 micron; HP; floating point coprocessor; high-frequency operation; industry standard SRAMs; integer processor; large configurable memory; novel processor; precision architecture-reduced instruction set computer; processor cache; single chip; static RAMs; superscalar PA-RISC design; three-level metal CMOS technology; Bandwidth; CMOS technology; Circuit synthesis; Computer architecture; Coprocessors; Frequency; Packaging; Pipelines; Process design; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2655-0

Type

conf

DOI

10.1109/CMPCON.1992.186696

Filename

186696