• DocumentCode
    2908927
  • Title

    A 16-context Optically Reconfigurable Gate Array

  • Author

    Nakajima, Mao ; Watanabe, Minoru

  • Author_Institution
    Electr. & Electron. Eng., Shizuoka Univ., Hamamatsu, Japan
  • fYear
    2009
  • fDate
    7-9 July 2009
  • Firstpage
    227
  • Lastpage
    230
  • Abstract
    Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. Therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. This paper presents the fastest 317-657 ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.
  • Keywords
    field programmable gate arrays; reconfigurable architectures; 16-context optically reconfigurable gate array; VLSI chip; bandwidth optical connection; dynamic reconfiguration; holographic memory; programmable gate array; reconfigurable gate array architecture; very large scale integration; virtual gate count; Circuits; Clocks; Computer aided instruction; Computer architecture; High speed optical techniques; Holographic optical components; Holography; Optical arrays; Reduced instruction set computing; Very large scale integration; Dynamic reconfiguration; Field Programmable Gate Array; Optically Reconfigurable Gate Array;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-specific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on
  • Conference_Location
    Boston, MA
  • ISSN
    2160-0511
  • Print_ISBN
    978-0-7695-3732-0
  • Electronic_ISBN
    2160-0511
  • Type

    conf

  • DOI
    10.1109/ASAP.2009.41
  • Filename
    5200037