DocumentCode
2908958
Title
Pinnacle-1: the next generation SPARC processor
Author
Vegesna, Raju
fYear
1992
fDate
24-28 Feb. 1992
Firstpage
152
Lastpage
156
Abstract
The Pinnacle-1 second-generation SPARCore module is described. This module has been designed to provide high-performance and low-cost systems. An architectural overview of the Pinnacle-1 SPARCore module is presented. It is noted that the Pinnacle-1 SPARCore module provides an elegant solution for easy upgradability from the current generation systems along with enhanced performance through the MILE (multiple instruction launch and execute) architecture.<>
Keywords
microprocessor chips; parallel architectures; parallel machines; MILE; Pinnacle-1 SPARCore module; Pinnacle-1 second-generation SPARCore module; architectural overview; easy upgradability; enhanced performance; high-performance; low-cost systems; multiple instruction launch and execute; Central Processing Unit; Clocks; Computer aided instruction; Decoding; Frequency synchronization; Pipeline processing; Random access memory; System performance; Trademarks; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2655-0
Type
conf
DOI
10.1109/CMPCON.1992.186701
Filename
186701
Link To Document