Title :
Performance issues for the 88110 RISC microprocessor
Author :
Phillip, Michael J.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
The Motorola 88110 RISC (reduced instruction set computer) microprocessor is a second-generation, superscalar implementation of the 88000 architecture that is capable of achieving extremely high-performance for a broad class of general-purpose and scientific applications. In order to attain this performance, however, a balance is needed between hardware and software. With the development of optimizing compilers and accurate simulation tools for the 88110 it has been possible to begin tuning 88110 performance long before a system becomes available for software development and experimentation. The author describes the compilation and simulation environments developed for the 88110, and summarizes a number of key performance issues for the processor.<>
Keywords :
microcomputers; performance evaluation; program compilers; reduced instruction set computing; virtual machines; 88000 architecture; Motorola 88110; RISC microprocessor; compilation environment; optimizing compilers; processor performance; reduced instruction set computer; simulation tools; software development; Application software; Computational modeling; Computer aided instruction; Computer architecture; Hardware; Microprocessors; Optimizing compilers; Programming; Reduced instruction set computing; Software performance;
Conference_Titel :
Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2655-0
DOI :
10.1109/CMPCON.1992.186703
