A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs

Author

Gulati, K. ; Peng, M. ; Pulincherry, A. ; Munoz, C. ; Lugin, M. ; Bugeja, A. ; Li, J. ; Chandrakasan, A.

Author_Institution

Engim Inc., Acton, MA, USA

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

515

Lastpage

518

Abstract

The 180MSPS, 13b CMOS pipelined ADC of a transceiver is implemented without a dedicated track-and-hold stage and utilizes a front-end 2.5b stage with matched MDAC/comparator tracking circuits. The ADC demonstrates ENOB of 10.6b at 15MHz and 9.7b at 100MHz. It employs a low-jitter delay-lock loop for its phasing. The dual I/Q 12b 180MSPS DACs show over 62dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); delay lock loops; digital-analogue conversion; integrated circuit design; pipeline processing; transceivers; 10.6 bit; 100 MHz; 12 bit; 13 bit; 15 MHz; 9.7 bit; CMOS analog baseband transceiver; MDAC circuits; Nyquist band; comparator tracking circuits; dynamic linearity enhancing architecture; low jitter delay-lock loop; pipelined CMOS ADC; Baseband; Capacitors; Circuits; Frequency; Linearity; Pipelines; Preamplifiers; Sampling methods; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568719

Filename

1568719