Title :
Alpha architecture and first implementation
Author :
Sites, R.L. ; Witek, R.T.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
Summary form only given. Alpha is a new 64-b RISC (reduced instruction set computer) architecture designed to facilitate superpipelined and superscalar implementations. EV4, the first implementation of the Alpha architecture, is a 200-MHz custom VLSI CPU with a peak issue rate of 400 MIPs. EV4 is implemented in Digital´s 0.75- mu m 3.3-V CMOS technology, contains 1.68 M transistors on a 16.8-mm*13.9-mm chip, and is packaged in a 431-pin PGA. The Alpha architecture, besides supporting a variety of integer and floating point data types, emphasizes pipelining, memory synchronization, and memory access. To facilitate application of the chip on a broad spectrum of applications, EV4 connects directly to an external writeback backup cache built from industry-standard static RAMs.<>
Keywords :
digital arithmetic; parallel architectures; pipeline processing; reduced instruction set computing; 200 MHz; 400 MIPS; 64 bits; Alpha; CMOS technology; Digital; EV4; PGA; RISC; VLSI CPU; external writeback backup cache; floating point data types; integer data types; memory access; memory synchronization; pipelining; random access memory; reduced instruction set computer; superpipelined; superscalar; CMOS technology; Electronics packaging; History; Prefetching; Read-write memory; Reduced instruction set computing; Synchronization; Very large scale integration;
Conference_Titel :
Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2655-0
DOI :
10.1109/CMPCON.1992.186711
