Title :
A digital clock and data recovery architecture for multi-gigabit/s binary links
Author :
Sonntag, Jeff ; Stonick, John
Author_Institution :
Synopsys, Inc., Hillsboro, OR, USA
Abstract :
In this paper we present a general architecture for digital clock and data recovery (CDR) for high speed binary links. The architecture is based on replacing the analog loop filter and VCO in a typical analog PLL-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Finally, measured results are presented that corroborate the modeled results.
Keywords :
clocks; phase detectors; phase locked loops; telecommunication links; VCO; analog PLL; analog loop filter; bang-bang phase detector; data recovery architecture; decimation effects; digital clock recovery architecture; digital components; high speed binary links; self-noise effects; Application specific integrated circuits; Charge pumps; Clocks; Detectors; Digital filters; Phase detection; Phase locked loops; Signal analysis; Signal processing; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568725
