Automatic dependency model generator for mixed-signal circuits

Dependency models are the basis of several important products for testability analysis, diagnosability analysis, and generation of optimal fault frees, including generation of dynamic test strategies based on current parameters and available resources. The problem with dependency models is that they are difficult to generate. We are developing a new software tool for automatic generation of dependency models. The approach is based on use of SPICE simulation. The preprocessor augments the SPICE netlist of the UUT (Unit Under Test) based on a failure-mode table. The result is an augmented netlist and a set of ICL (interactive Command Language) commands to automatically modulate the structures and/or values of each component for different failure modes. Finally a post-processor analyses the fault simulation results and extracts a dependency model for the system. This tool solves the most time-consuming (hence costly) problem in dependency model-based testability analysis-generating the dependency model from the circuit. This paper focuses on the theory strengths, and weaknesses of the tool, and describes approaches to build the next generation of more capable tools for automatic generation of dependency models