DocumentCode
2909146
Title
High performance single chip VAX microprocessor
Author
Uhler, M.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1992
fDate
24-28 Feb. 1992
Firstpage
215
Abstract
Summary form only given. The author describes NVAX, a high-performance, single-chip implementation of the VAX architecture, which is fully compatible with previous VAX implementations. The chip is used in the VAX 6000 model 600 and VAX 4000 model 500 systems. In its highest performance version NVAX runs at 83.3 MHz, and delivers 40.4 SPECmarks and 83.6 transactions per second on the TPC-A benchmark. NVAX is implemented in Digital´s 0.75- mu m CMOS 3.3-V technology, contains 1.3 M transistors, and is packaged in a 339-pin PGA. The NVAX design uses RISC (reduced instruction set computer) principles to improve performance. Included on the chip are a 96-entry, fully associative translation buffer, a 2-KB direct-mapped virtual instruction cache, an 8-KB, 2-set associative instruction and data cache and a writeback backup cache controller that interfaces to tag and data RAMs on the module.<>
Keywords
DEC computers; microcomputers; microprocessor chips; performance evaluation; reduced instruction set computing; 2 KB; 8 KB; 83.3 MHz; CMOS; NVAX; PGA; RISC; TPC-A benchmark; VAX 4000 model 500; VAX 6000 model 600; direct-mapped virtual instruction cache; fully associative translation buffer; reduced instruction set computer; single chip VAX microprocessor; writeback backup cache controller; CMOS technology; Decoding; Electronics packaging; Microprocessors; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Semiconductor device modeling; Size control;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2655-0
Type
conf
DOI
10.1109/CMPCON.1992.186712
Filename
186712
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