Notice of Violation of IEEE Publication Principles9.953-12.5GHz 0.13μm CMOS LC VCO using a high resolution calibration and a constant gain varactor

Notice of Violation of IEEE Publication Principles

"9.953-12.5GHz 0.13μm CMOS LC VCO Using a High Resolution Calibration and a Constant Gain Varactor"
by A. Maxim and C. Turinici,
in the Proceedings of the IEEE Custom Integrated Circuits Conference, 2005

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the coauthor\´s name was fabricated by Adrian Maxim and added to the paper. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A multi-standard LC oscillator for 10Gb/s SERDES applications was realized in a 0.13μm CMOS process. The phase noise was reduced by using a high quality factor bond wire inductor in conjunction with a high resolution calibration network that brings the oscillating frequency to within 0.1% of the target value, reducing thus the oscillator gain below 110MHz/V. A low gain ripple varactor was realized with multiple parallel connected accumulation MOS capacitors having the bias voltages offset such that their peak gain points are uniformly distributed over the control voltage range. The supply pushing w- s minimized by cancelling the gate capacitance positive voltage coefficient with the negative coefficient of an appropriately sized drain diffusion capacitance. A dual regulator architecture was used to ensure the low noise and high PSRR requirements.