HP´s link interface chipset for Serial-HIPPI

Author

McFarland, W. ; Walker, R. ; Stout, C. ; Wu, J. ; Lai, B. ; Kwan, G. ; Yen, C.

fYear

1992

fDate

24-28 Feb. 1992

Firstpage

229

Lastpage

233

Abstract

A link interface chipset that conforms to the Serial-HIPPI (High-Performance Parallel Interface) specification is presented. The chipset contains all portions of the link interface and link control functions specified in Serial-HIPPI. The simple additional circuitry required to create a complete Serial-HIPPI link using this chipset is detailed. The two-chip set can also serve as a general-purpose link with no additional circuitry. It transfers parallel data across a serial channel at rates from 960 Mb/s to 1440 Mb/s. It provides automatic link startup and continuous frame synchronization, and requires no adjustments or off-package circuitry.<>

Keywords

data communication equipment; local area networks; microprocessor chips; network interfaces; 1440 Mbit/s; 960 Mbit/s; Hewlett-Packard; High-Performance Parallel Interface; Serial-HIPPI; automatic link startup; continuous frame synchronization; link control functions; link interface chipset; specification; Circuits; Clocks; Coaxial cables; Computer peripherals; Costs; Data communication; Optical fiber cables; Optical fibers; Transmitters; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2655-0

Type

conf

DOI

10.1109/CMPCON.1992.186716

Filename

186716