Title :
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking
Author :
Loke, A.L.S. ; Barnes, R.K. ; Wee, T.T. ; Oshima, M.M. ; Moore, C.E. ; Kennedy, R.R. ; Barnes, J.O. ; Zimmer, R.A. ; Arave, K.L. ; Pang, H.H.M. ; Cynkar, T.E. ; Volz, A.M. ; Pfiester, J.R. ; Martin, R.J. ; Miller, R.H. ; Hood, D.A. ; Motley, G.W. ; Rojas,
Author_Institution :
Agilent Technol., Fort Collins, CO, USA
Abstract :
A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized using an area-efficient LC-VCO with helical inductors and inversion-mode nFET varactors for 45% tuning range. The PLL exhibits 0.81 ps rms jitter at 10.0 Gb/s. Technology considerations for improving design manufacturability, tuning range, and jitter performance are addressed.
Keywords :
CMOS integrated circuits; inductors; jitter; phase locked loops; programmable filters; transmitters; varactors; voltage-controlled oscillators; 0.81 ps; 1 to 10 Gbit/s; 90 nm; CMOS; LC-VCO; charge-pump PLL; closed-loop bandwidth; design manufacturability; dual-path loop filter; helical inductors; inversion-mode varactors; jitter performance; low-jitter PLL; nFET varactors; programmable filter; transmitter clocking; tuning range; Bandwidth; Charge pumps; Clocks; Filters; Jitter; Phase locked loops; Proportional control; Semiconductor device modeling; Transmitters; Tuning;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568728
