Title :
Minimizing Cu Contamination Risk and Establishment of Control Limit for Floor Surface When Running Both Al and Cu in a Shared Production Line
Author :
Bakar, H.A. ; Awang, Zaiki ; Razali, Wan Ab Aziz Wan
Author_Institution :
Univ. Teknologi MARA, Shah Alam
Abstract :
As interconnect manufacturers move to copper (Cu) metallization for their most advanced product, contamination control presents big challenges. These include control of Cu contamination within the Cu processing area (Cu-dedicated area) and aluminium (Al) processing area (Cu-free area). This study aims at controlling Cu level on the floor surfaces of Cu-dedicated and Cu-free areas inside a semiconductor wafer fab. This is because Cu is a heavy metal and Cu impurities will most probably be located on the floor. Several sampling locations for both of these areas are selected and the Cu level measured by using total X-ray fluorescence (TXRF) methodology. This paper presents results on the use of this method to identify and verify Cu contamination by assessing the density of Cu elements. The results from this methodology will be used to develop a control limit, which will serve as a reference to understand the safe limit of Cu level in a microelectronic fabrication facility. A control limit for both Cu-dedicated and free area is presented in quantitative value in atom/cm2 unit, which is represented as baseline information from periodic monitoring. Analysis of TXRF in this study has shown that Cu results in a level of 1times1012 atom/cm2. From these results we conclude that a control limit for Cu-dedicated area indicated a higher level of Cu compared with Cu-free area since more Cu impurities are present in the Cu processing area. The control limit level of 1times1012 atom/cm2 is proposed herewith as a guide and reference limit to monitor Cu level on the floor inside a semiconductor wafer fab. This guideline will provide a quick response solution even to small fluctuations of Cu level.
Keywords :
aluminium; contamination; copper; integrated circuit interconnections; integrated circuit manufacture; semiconductor device manufacture; semiconductor device metallisation; wafer-scale integration; Al; Cu; contamination risk minimization; copper metallization; floor surface control limit; interconnect manufacturers; microelectronic fabrication facility; semiconductor wafer fab; shared production line; total X-ray fluorescence methodology; Aluminum; Area measurement; Copper; Manufacturing; Metallization; Monitoring; Production; Sampling methods; Semiconductor impurities; Surface contamination; Cu contamination; TXRF methodology;
Conference_Titel :
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-0797-2
Electronic_ISBN :
978-1-4244-0797-2
DOI :
10.1109/ISICIR.2007.4441847