Scheduling and simulation of neural nets on a DSP accelerator

Author

Mirchandani, Gagan ; Pegram, Robert B., III ; Stone, Frederic L. ; Twombly, Peter

Author_Institution

Dept. of Comput. Sci. & Electr. Eng., Vermount Univ., Burlington, VT, USA

fYear

1990

fDate

3-6 Apr 1990

Firstpage

1771

Abstract

A description is given of the Software Development System (SDS), which consists of a preprocessor and a general-purpose scheduler, and which has been used to generate schedules for two-layer fully connected neural networks. The particular structure (precedence graph) of the code of the back-propagation algorithm which is used to generate parallel code is described. Also described is the prototype ADSP-2100 parallel processing system that has been built and on which some of the smaller size neural networks have been implemented. Cycle count for scheduling the back-propagation algorithm on various sizes of neural networks and two digital signal processing (DSP) architectures and associated throughput rates obtained are given. Cycle counts for computation (with concurrent data communication) and communication only are also obtained

Keywords

computerised signal processing; development systems; neural nets; parallel algorithms; scheduling; software engineering; ADSP-2100 parallel processing system; DSP accelerator; Software Development System; back-propagation algorithm; concurrent data communication; digital signal processing; general-purpose scheduler; neural nets; precedence graph; preprocessor; throughput rates; Acceleration; Computer architecture; Digital signal processing; Neural networks; Parallel processing; Processor scheduling; Programming; Prototypes; Scheduling algorithm; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.115828

Filename

115828