• DocumentCode
    2909321
  • Title

    Architecture and performance of a new arithmetic unit for the computation of elementary functions

  • Author

    Meyer, R. ; Mehling, R.

  • Author_Institution
    Lehrstuhl fuer Nachritentech., Erlangen-Nurnberg Univ., West Germany
  • fYear
    1990
  • fDate
    3-6 Apr 1990
  • Firstpage
    1783
  • Abstract
    The design of a recursive arithmetic unit for evaluation of elementary functions is discussed. Two distinct classes of binary algorithms are implemented. One class is based on a generalization of the compensated CORDIC method. The other class, which replaces the linear CORDIC case, is based on the convergence transformations in connection with multiple bit encoding techniques. The proposed hardware solution provides a significant speed advantage over software calculations and more flexibility than special units designed only for a subset of these functions
  • Keywords
    convergence; digital arithmetic; encoding; arithmetic unit; binary algorithms; compensated CORDIC method; convergence transformations; elementary functions; hardware solution; multiple bit encoding techniques; speed advantage; Arithmetic; Computer architecture; Digital signal processing; Digital signal processing chips; Encoding; Floating-point arithmetic; Gold; Hardware; Polynomials; Signal processing algorithms; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on
  • Conference_Location
    Albuquerque, NM
  • ISSN
    1520-6149
  • Type

    conf

  • DOI
    10.1109/ICASSP.1990.115833
  • Filename
    115833