Title :
A yield and speed enhancement scheme under within-die variations on 90nm LUT array
Author :
Katsuki, Kazuya ; Kotani, Manabu ; Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution :
Graduate Sch. of Informatics, Kyoto Univ.
Abstract :
In this paper, we propose a yield and speed enhancement scheme using a reconfigurable device. An LUT array LSI is fabricated on a 90nm process to measure process variations of LUTs. D2D and WID variations are clearly observed. Reconfiguration using the measurement process variations boosts yield and also increases the average operating speed by 4.1%. In addition, it is proved that expansion of WID variations make the proposed method more effective
Keywords :
integrated circuit design; integrated circuit measurement; integrated circuit yield; large scale integration; reconfigurable architectures; table lookup; 90 nm; LUT array LSI; measurement process variations; reconfigurable device; speed enhancement scheme; within-die variations; yield enhancement scheme; Degradation; High K dielectric materials; Informatics; Integrated circuit measurements; Large scale integration; Manufacturing; Semiconductor device measurement; Table lookup; Timing; Velocity measurement;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568739
