Title :
A Differential Output Delay Cell Based Ring VCO for Improved Jitter Performance
Author :
Singh, Gautam Kumar ; Jamadagni, H.S.
Author_Institution :
Pulsecore Semicond. (I) Pvt Ltd., Bangalore
Abstract :
This paper presents a multi-stage 3.3 V ring VCO in 0.35 mum CMOS technology with differential control and complimentary outputs based on complimentary latch and pass transistor input stage. The differential structure helps in rejecting the substrate and supply noise commonly. It has improved supply noise rejection. Jitter and phase noise due to substrate and supply noise is discussed and the results has been compared with the previous reported VCO architectures.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit noise; jitter; phase noise; voltage-controlled oscillators; CMOS technology; complimentary latch and pass transistor; differential control; differential output delay cell; jitter performance improvement; phase noise; ring voltage-controlled oscillators; size 0.35 mum; voltage 3.3 V; 1f noise; Circuit noise; Clocks; Delay; Frequency; Jitter; Phase locked loops; Phase noise; Semiconductor device noise; Voltage-controlled oscillators; CMOS; Jitter; PLL; Substrate-noise; VCO;
Conference_Titel :
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-0797-2
Electronic_ISBN :
978-1-4244-0797-2
DOI :
10.1109/ISICIR.2007.4441861
