Title :
Software-based fault tolerance for the Maestro many-core processor
Author :
Walters, John Paul ; Kost, Robert ; Singh, Karandeep ; Suh, Jinwoo ; Crago, Stephen P.
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Marina Del Rey, CA, USA
Abstract :
The current generation of radiation-hardened general-purpose processors, such as the RAD750, lag far behind their commercial counterparts in terms of performance. To combat this, a new many-core processor was designed that would allow space applications to leverage up to 49 general-purpose processing cores for high performance space applications. The Maestro processor, based on Tilera´s TILE64 chip, is the result of this effort. Maestro is rad-hard by design, but there is still the possibility of both hardware and software errors.
Keywords :
aerospace computing; multiprocessing systems; software fault tolerance; Maestro many-core processor; Tilera TILE64 chip; application specific fault tolerance; distributed heartbeat implementation; general purpose processing cores; high performance space application; hybrid fault tolerance; kernel-level checkpoint; kernel-level rollback; radiation tolerance; software based fault tolerance; thread-level redundancy; Fault tolerance; Fault tolerant systems; Heart beat; Instruction sets; Libraries; Tiles;
Conference_Titel :
Aerospace Conference, 2011 IEEE
Conference_Location :
Big Sky, MT
Print_ISBN :
978-1-4244-7350-2
DOI :
10.1109/AERO.2011.5747448
