Title :
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology
Author :
Guilar, Nathaniel J. ; Lau, Pak-Kim ; Hurst, Paul J. ; Lewis, Stephen H.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Davis Univ., USA
Abstract :
A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35μm CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The equalizer is fully differential with a 4-tap transfer function. The equalizer consumes 19.5 mW at 200 MS/s and occupies an active area of 1.3mm2.
Keywords :
CMOS integrated circuits; FIR filters; equalisers; network topology; passive filters; switched capacitor filters; transfer functions; 0.35 micron; 19.5 mW; CMOS circuits; FIR equalizer; binary data signal; finite-impulse response equalizer; nonlinear parasitic capacitance; passive switched-capacitor; ternary data signal; time-interleaved channels; time-interleaved topology; transfer function; Circuit topology; Equalizers; Equations; Finite impulse response filter; Intersymbol interference; Parasitic capacitance; Sampling methods; Switches; Switching circuits; Transfer functions;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568749
