DocumentCode :
2909666
Title :
A Top-Down Design Verification Based on Reuse Modular and Parametric Behavioral Modeling for Subranging Pipelined Analog-to-Digital Converter
Author :
Wang, J. ; Siek, L. ; Filippi, R. ; Ng, K.A.
Author_Institution :
Nanyang Technol. Univ., Singapore
fYear :
2007
fDate :
26-28 Sept. 2007
Firstpage :
378
Lastpage :
381
Abstract :
This paper proposes a new approach to high speed pipelined A/D converter design. This technique combines a known subranging technique into pipelined architecture. A 8-bit 100 MSample/s subranging pipelined analog-to-digital converter (ADC) is implemented using this technique. The calibration techniques used are namely digital error correction, redundancy, and coarse and fine synchronization. To validate the proposed ADC, a top-down design methodology based on modular and parametric behavioral components is adopted. It supports a design process where non-ideal effects are incorporated in an incremental way, allowing easy architectural selection with fast and accurate simulations. The behavioral models are written in standard hardware description language, Verilog-AMS.
Keywords :
analogue-digital conversion; calibration; hardware description languages; pipeline processing; Verilog-AMS; analog-to-digital converter design; calibration technique; digital error correction; parametric behavioral modeling; pipelined architecture; standard hardware description language; subranging technique; top-down design verification method; Analog-digital conversion; Costs; Design methodology; Error correction; Hardware design languages; High speed integrated circuits; Pipeline processing; Process design; Signal design; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-0797-2
Electronic_ISBN :
978-1-4244-0797-2
Type :
conf
DOI :
10.1109/ISICIR.2007.4441877
Filename :
4441877
Link To Document :
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