Title :
Timing Analysis of a Protected Operating System Kernel
Author :
Blackham, Bernard ; Shi, Yao ; Chattopadhyay, Sudipta ; Roychoudhury, Abhik ; Heiser, Gernot
Author_Institution :
NICTA, Univ. of New South Wales, Sydney, NSW, Australia
fDate :
Nov. 29 2011-Dec. 2 2011
Abstract :
Operating systems offering virtual memory and protected address spaces have been an elusive target of static worst-case execution time (WCET) analysis. This is due to a combination of size, unstructured code and tight coupling with hardware. As a result, hard real-time systems are usually developed without memory protection, perhaps utilizing a lightweight real-time executive to provide OS abstractions. This paper presents a WCET analysis of seL4, a third-generation micro kernel. seL4 is the world´s first formally-verified operating-system kernel, featuring machine-checked correctness proofs of its complete functionality. This makes seL4 an ideal platform for security-critical systems. Adding temporal guarantees makes seL4 also a compelling platform for safety- and timing-critical systems. It creates a foundation for integrating hard real-time systems with less critical time-sharing components on the same processor, supporting enhanced functionality while keeping hardware and development costs low. We believe this is one of the largest code bases on which a fully context-aware WCET analysis has been performed. This analysis is made possible due to the minimalistic nature of modern micro kernels, and properties of seL4´s source code arising from the requirements of formal verification.
Keywords :
formal verification; operating system kernels; real-time systems; safety-critical software; security of data; source coding; OS abstractions; WCET analysis; formal verification; hard real-time systems; machine-checked correctness proofs; memory protection; operating system kernel protection; protected address spaces; seL4; security-critical systems; source code; static worst-case execution time analysis; third-generation microkernel; timing analysis; timing-critical systems; unstructured code; virtual memory; Analytical models; Hardware; Kernel; Pipelines; Real time systems; Switches; Operating system kernels; Real time systems; Software verification and validation;
Conference_Titel :
Real-Time Systems Symposium (RTSS), 2011 IEEE 32nd
Conference_Location :
Vienna
Print_ISBN :
978-1-4577-2000-0
DOI :
10.1109/RTSS.2011.38