HLS based DSP optimization with ASIC RTL libraries

Author

Isoaho, Jouni ; Öberg, Johnny ; Hemani, Ahmed ; Tenhunen, Hannu

Author_Institution

Signal Process. Lab., Tampere Univ. of Technol., Finland

fYear

1994

fDate

1994

Firstpage

218

Lastpage

225

Abstract

In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach

Keywords

high level synthesis; ASIC RTL libraries; ASIC development; DSP optimization; Lsi10k series; Matlab; SYNT; Synopsys; Xilinx 4000 series; architecture selection; code optimizations; design environments; high level synthesis; parameter optimization; register transfer level; structure recognition; Application specific integrated circuits; Design optimization; Digital signal processing; Field programmable gate arrays; Filters; High level synthesis; Libraries; Process design; Signal processing algorithms; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VII, 1994., [Workshop on]

Conference_Location

La Jolla, CA

Print_ISBN

0-7803-2123-5

Type

conf

DOI

10.1109/VLSISP.1994.574746

Filename

574746