A Clock System for High Speed and Low Power Parallel Link

A clock system using PLL for high speed and low power parallel link is presented. The PLL is designed with a voltage regulator which provides a clear supply voltage for the noise sensitive blocks such as voltage controlled oscillator in the noisy environment. A new method is explored to generate clocks for dynamic frequency switching of the high speed link which works in source-synchronous style. This method can switch the working frequency of the I/O circuits quickly without modifying the state of the PLL block. Especially it is very simple to implement with small penalty. As a whole, a high speed and low power parallel link transmitter has been designed and fabricated in the 0.18 um CMOS technology.