An ASIC implementation of JPEG2000 codec

This paper proposed an ASIC implementation of JPEG2000 codec. In discrete wavelet transform (DWT) part, spatial combinative lifting algorithm (SCLA) based DWT with both 5/3 and 9/7 filters is proposed to reduce 50% and 42% multiplication computations respectively compared with the conventional lifting based implementation (LBI). In embedded block coding with optimized truncation (EBCOT) part, a dynamic memory control (DMC) scheme is proposed in Tier-1 to minimize the scale of the on-chip wavelet coefficient storage, and an architecture of Tier-2 is proposed to considerably eliminate the iteration of the rate-distortion (RD) truncation and accurately control the compression bit-rate (with 95% precision). This codec is capable of JPEG2000 compression/decompression with a 1280×1024 pixel (YUV422 full color) at 20frames/s employing 100MHz working clock. Power consumption is 465mW at 1.8V and 100MHz.