An (8158,7136) low-density parity-check encoder

Author

Miles, L. ; Gambles, J. ; Maki, G. ; Ryan, W. ; Whitaker, S.

Author_Institution

Center for Adv. Microelectron. & Biomolecular Res., Idaho Univ., Post Falls, ID, USA

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

699

Lastpage

702

Abstract

Low-density parity-check codes achieve coding performance which approaches the Shannon limit. Based on a novel method for deriving regular quasi-cyclic sub-codes, a radiation tolerant encoder was implemented in 0.25μm CMOS. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1,492 flip flops along with a programmable 21-bit look-ahead scheme are used to achieve a 1 Gb/s data throughput. A comparable two-stage encoder requires 8,176 flip flops.

Keywords

CMOS logic circuits; cyclic codes; flip-flops; matrix algebra; parity check codes; polynomials; radiation hardening (electronics); 0.25 micron; 1 Gbit/s; 21 bit; CMOS radiation tolerant encoder; Shannon limit; coding performance; flip flops; generator polynomial reconstruction; look-ahead scheme; low-density parity-check codes; low-density parity-check encoder; parity register; partial product multiplication; quasi-cyclic sub-codes; two-stage encoder; Data communication; Decoding; Error correction codes; Linear code; Memory; Microelectronics; Parity check codes; Polynomials; Throughput; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568764

Filename

1568764