A virtual test-bench for analog circuit testability analysis and fault diagnosis

Are fault simulation techniques feasible and effective for fault diagnosis of analog circuits? In this paper, we investigate these issues via a software tool which can generate testability metrics and diagnostic information for analog circuits represented by SPICE descriptions. This tool, termed the virtual test bench (VTB), incorporates three different simulation-based techniques for fault detection and isolation. The first method is based on the creation of fault-test dependency models, while the other two techniques employ machine learning principles based on the concepts of: (1) Restricted Coloumb Energy (RCE) Neural Networks, and (2) Learning Vector Quantization (LVQ). Whereas the output of the first method can be used for the traditional off-line diagnosis, the RCE and LVQ models render themselves more naturally to on-line monitoring, where measurement data from various sensors is continuously available. Since it is well known that analog faults and test measurements are affected by component parameter variations, we have also addressed the issues of robustness of our fault diagnosis schemes. Specifically, we have attempted to answer the questions regarding fixing of test measurement thresholds, obtaining the minimum number of Monte-Carlo runs required to stabilize the measurements and their deviations, and the effect of different thresholding schemes on the robustness of fault models. Although fault-simulation is a powerful technique for analog circuit testability analysis, its main shortcomings are the long simulation time, large volume of data and the fidelity of simulators in accurately modeling faults. We have plotted the simulation time and volume of data required for a range of circuit sizes to provide guidance on the feasibility and efficacy of this approach