A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators

Phase-locked loops are used in a variety of applications, such as frequency synthesis/clock and data recovery. The nature of these applications requires high accuracy for predicting the PLL nonlinearities and dynamics during the design process, which thereby requires prohibitively expensive transistor-level simulation. In this paper we propose a compact behavioral model for voltage-controlled oscillators, which are the key components of PLLs, and the most difficult to macromodel due to their dynamic, large-scale nonlinear behavior. Unlike previous works, our approach follows a systematic modeling of nonlinear dynamics in a topology independent manner. We demonstrate that our model can reduce the system-level simulation runtime significantly without sacrificing the required accuracy.