A Pseudo-Random Program Generator for Processor Functional Verification

This paper presents an ISA model-based pseudorandom program generator, called as VirgoASM, for functional verification of RISC3200 processor. The kernel parts of VirgoASM are instruction generating models and test templates. In order to ensure the complete instruction generating space and the legality and validity of generated single instruction, instruction opcode and operand sets are built according to the function, syntax format and semantic requirements of instructions. Then 17 instruction generating models are constructed based on the Cartesian product of instruction opcode and operand sets. According to instruction generating models and verification plans, various types of test templates are created to guarantee the quality requirement of generated instruction sequences. At last, we demonstrate that how to use VirgoASM to generate test programs.