Aliasing in multiple-valued test data compaction

The possibility of using multivalued instead of binary linear multiple input shift registers (MISRs) for output compaction of multiple-valued logic circuits is discussed. The use of multivalued MISRs avoids the need for decoding the signals. A framework for examining aliasing in multiple-valued circular MISRs is presented. The exact aliasing probability is obtained for ternary and quaternary MISRs under an independent error model for an arbitrary test length. It is shown that multivalued MISRs perform better than their binary counterparts