A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware

This paper addresses the problem of choosing different word-lengths for each functional unit in fixed-point implementations of DSP algorithms. A symbolic-noise analysis method is introduced for high-level synthesis of DSP algorithms in digital hardware, together with a vector evaluated genetic algorithm for multiple objective optimization. The ability of this method to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated by example designs.