A low-complexity bit-serial DCT/IDCT architecture

Author

Fettweis, Gerhard ; Chiu, Josef ; Fraenkel, Bernard

Author_Institution

Teknekron Commun. Syst., Berkeley, CA, USA

Volume

1

fYear

1993

fDate

23-26 May 1993

Firstpage

217

Abstract

A novel DCT/IDCT (discrete cosine transform/inverse DCT) dataflow architecture is presented allowing the efficient implementation of one hardware unit, which has only positive-valued multiplier coefficients and can be switched to perform either the DCT or the IDCT. The MSB (most significant bit)-first carry-save arithmetic introduced allows the design of extremely efficient solutions with low processing delay and high precision, which support medium-to-low-speed transform rates. The results of the H.261 precision compliant CMOS realization prove the hardware efficiency of this architecture

Keywords

CMOS digital integrated circuits; carry logic; computational complexity; data flow graphs; discrete cosine transforms; inverse problems; CMOS; carry-save arithmetic; dataflow architecture; discrete cosine transform; hardware efficiency; inverse DCT; precision; processing delay; CMOS integrated circuits; Computer architecture; Delay; Discrete cosine transforms; Fast Fourier transforms; Fourier transforms; Frequency; Hardware; Image coding; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 1993. ICC '93 Geneva. Technical Program, Conference Record, IEEE International Conference on

Conference_Location

Geneva

Print_ISBN

0-7803-0950-2

Type

conf

DOI

10.1109/ICC.1993.397260

Filename

397260