A 90nm power optimization methodology and its´ application to the ARM 1136SF-S microprocessor

Author

Khan, A. ; Watson, P. ; Kuo, G. ; Le, D. ; Nguyen, T. ; Yang, S. ; Bennet, P. ; Huang, P. ; Gill, J. ; Wang, D. ; Ahmed, I. ; Tran, P. ; Mak, H. ; Kim, O. ; Martin, F. ; Fan, Y. ; Ge, D. ; Kung, J. ; Shek, V.

Author_Institution

Cadence Design Syst., Inc., San Jose, CA

fYear

2005

fDate

21-21 Sept. 2005

Firstpage

771

Lastpage

774

Abstract

An electrical and physical design power optimization methodology and design techniques developed to create an ARM 1136SF-S microprocessor in 9Onm standard CMOS are presented. A 40% reduction in power dissipation has been achieved while maintaining a 355 MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon

Keywords

CMOS integrated circuits; integrated circuit design; microprocessor chips; 355 MHz; 90 nm; ARM 1136SF-S microprocessor; IC design methodology; IC design technique; clock design; clock distribution; clock rate; design validation; electrical design; functional design; physical design; power dissipation; power distribution; power optimization; power reduction; signal integrity; standard CMOS; Clocks; Computer architecture; Coprocessors; Design methodology; Energy efficiency; Microprocessors; Optimization methods; Power dissipation; Signal design; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568782

Filename

1568782