Title :
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies
Author :
Chen, Yiran ; Li, Hai ; Roy, Kaushik ; Koh, Cheng-Kok
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
Abstract :
A novel on-chip Decoupling Capacitor (Decap) design - Gated Decoupling Capacitor (GDecap) - is proposed to minimize the leakage power dissipation associated with present-day on-chip decoupling capacitors. Experiments on the application of GDecap in an 8-way clock-gated cluster pipeline show that on average, 41.7% Decap leakage power is improved, with only 0.037% worst-case performance degradation, at 70nm technology node. Around 5.36% area overhead in Decap area is incurred, compared to the conventional Decap deployment
Keywords :
capacitors; leakage currents; nanoelectronics; system-on-chip; 70 nm; 8-way clock-gated cluster pipeline; gate leakage control; gated Decap; leakage power dissipation; on-chip decoupling capacitor; scaled technology; worst-case performance degradation; Capacitors; Clocks; Gate leakage; Leakage current; Logic; Pipelines; Power dissipation; Power supplies; Threshold voltage; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568783
