Title :
An application of the p-valued input, q-kind-valued output logic to the synthesis of the p-valued logical networks
Author_Institution :
Dept. of Inf. Network Eng., Aichi Inst. of Technol., Toyota, Japan
Abstract :
The concept of p-valued input, q-kind-valued output logic (2⩽q⩽p, 3⩽p) is proposed. Low-cost p-valued logical networks can be realized by selecting the appropriate value q. The condition for s-(p,q)-logical completeness is derived (0⩽s⩽q). Some relationships between the s and the logical manifold are observed. It is found that the logical manifold increases rather radically as s becomes small
Keywords :
logic circuits; logic design; many-valued logics; logical manifold; p-valued input; p-valued logical networks; q-kind-valued output logic; s-(p,q)-logical completeness; Costs; Hardware; Logic; Network synthesis; Pins; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
Conference_Location :
Sendai
Print_ISBN :
0-8186-2680-1
DOI :
10.1109/ISMVL.1992.186787
