Author :
Venkata, Ramanand ; Chan, Vinson ; Ton, Binh ; Lee, Chong ; Ngo, Huy ; Kabani, Malik ; Nguyen, Tam ; Zaliznyak, Arch ; Xue, Ning ; Shen, Steven ; Zheng, Michael ; Lai, Michael ; Park, Steve ; Chan, Lana ; Vijayaraghavan, Divya ; Lam, John ; Patel, Rakesh
Abstract :
Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be bounded intelligently. Major architectural enhancements were necessary instead of a simple performance upgrade of the previous Hard IP. Verification complexity mandated design and verification re-use. Emulation and vendor soft IF interoperability testing was another strategy employed for first silicon success
Keywords :
IP networks; embedded systems; field programmable gate arrays; integrated circuit design; integrated circuit testing; protocols; system-on-chip; 0.622 to 6.375 Gbit/s; FPGA; IF interoperability testing; SOC; emulation; multi-protocol embedded PCS IP; multi-protocol serial interface physical layer; next-generation embedded hard IP; vendor soft; verification complexity mandated design; verification re-use; Emulation; Field programmable gate arrays; Memory management; Optical packet switching; Optical switches; Personal communication networks; Physical layer; Silicon; Technological innovation; Testing;
