Title :
A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process
Author :
Muhammad, K. ; Ho, Y.C. ; Mayhugh, T. ; Hung, C.-M. ; Jung, T. ; Elahi, I. ; Lin, C. ; Deng, I. ; Fernando, C. ; Wallberg, J. ; Vemulapalli, S. ; Larson, S. ; Murphy, T. ; Leipold, D. ; Cruise, P. ; Jaehnig, J. ; Lee, M.-C. ; Staszewski, R.B. ; Staszewski
Author_Institution :
Texas Instruments Inc., Dallas, TX
Abstract :
We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing to down convert, down- sample, filter and analog-to-digital convert the received signal. An auxiliary feedback is provided at the mixer output that can linearize the entire receive chain. The receiver meets a sensitivity of -110 dBm at 60 mA in a 1.4V digital CMOS process
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital phase locked loops; microprocessor chips; transceivers; 1.4 V; 60 mA; 90 nm; RF built-in self test; RF sampling; all-digital PLL; analog-to-digital converter; auxiliary feedback; dedicated ARM processor; digital CMOS; discrete time quad-band GSM/GPRS receiver; discrete-time analog signal processing; memory; power management; quad-band receiver; single-chip GSM transceiver; transmitter; Automatic testing; CMOS process; Energy management; GSM; Ground penetrating radar; Memory management; Radio frequency; Signal processing; Signal sampling; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568792
