Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems

Author

Kim, Kyung Ki ; Huang, Jing ; Kim, Yong-Bin ; Lombardi, Fabrizio ; Choi, Minsu

Author_Institution

Northeastern Univ., Boston

fYear

2007

fDate

1-3 May 2007

Firstpage

1

Lastpage

4

Abstract

This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems. Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed.

Keywords

VLSI; high-speed integrated circuits; integrated circuit modelling; intersymbol interference; timing jitter; IO channels; ISI; VLSI systems; high speed channels; inter-symbol interference; jitter classification; jitter injection method; timing jitter; 1f noise; Analytical models; Computational modeling; Computer simulation; Data systems; Gaussian distribution; Instrumentation and measurement; Intersymbol interference; Timing jitter; Very large scale integration; Duty Cycle Distortion; Inter-Symbol Interference; Jitter Components; Periodic Jitter; Random Jitter; Serial Data Systems; Timing Jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2007. IMTC 2007. IEEE

Conference_Location

Warsaw

ISSN

1091-5281

Print_ISBN

1-4244-0588-2

Type

conf

DOI

10.1109/IMTC.2007.379345

Filename

4258187