Area-efficient implication circuits for very dense Lukasiewicz logic arrays

A one-diode circuit for negated implication is derived from a 12-transistor Lukasiewicz implication circuit. The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower LLA contains 36000 implications in an area that previously held 92 implications; the three-transistor LLA contains 1990 implications. Both LLAs double the number of inputs per pin on the IC package. Very dense LLAs make LLA-based architectures practical. As an example, an LLA retina that detects edges in 15 ns is described