Simulation-based functional test generation for embedded processors

Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key to develop a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the growth in design size. This work proposes a functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions. One is called Boolean learning to be applied on random logic and the other is called arithmetic learning to be applied on datapath modules. We demonstrate the effectivenesses and discuss the limitations of these techniques through experiments on benchmark circuits. We validate the overall test generation methodology based on the OpenRISC 1200 microprocessor.