Establishing latch correspondence for embedded circuits of PowerPC microprocessors

We present a latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondences for latches (potentially nonscanable) in complex state machines having cyclic dependencies. Our methodology not only answers latch correspondence, but also provides polarity of the correspondence. This is a major advantage over earlier latch mapping algorithms. Experimental results obtained on embedded circuits from live PowerPCreg design projects have shown that our technique fares better than a leading vendor tool in mapping latches - in both quantitative (more latches mapped) and performance (time/memory used) aspects